Extensible Processing Platforms: Giving Designers the Best of Both Worlds

Creating a new field programmable gate array is no small feat. FPGA vendors spend tens-of-thousands of man-hours simply researching markets to determine the feature set a given device will require and the silicon process that they will use to manufacture the device. This starts years before they embark on the ever more difficult task of actually designing the IC and the software to allow users to program it.

While creating a next-generation FPGA is difficult, creating a device that combines a microprocessor and programmable logic on the same device is even more daunting. Vendors not only have to figure out the most efficient way to integrate programmable logic with a microprocessor in a tiny square of silicon, they must also create an infrastructure that allows users to quickly and easily program both the programmable logic and on-chip microprocessor portions of the device. For silicon vendors, the Holy Grail is to create a device that appeals not only to traditional FPGA users but to embedded system architects and software programmers as well. A new class of device called an Extensible Processing Platform (EPP) is making great strides on this journey.

Hard IP and Soft IP

Implementing microprocessors on FPGAs isn’t new. In fact, for almost two decades now FPGA vendors have offered soft cores (silicon intellectual property, commonly called IP) that users can program (with logic synthesis and place and route tools) into the programmable logic in FPGAs. About a decade ago, FPGA vendors took that a step further and designed microprocessor hard cores — PowerPC, ARM, and MIPs processors — into the silicon alongside traditional programmable logic blocks. Both soft IP and hard IP approaches have their advantages and disadvantages.

Implementing soft IP into an FPGA offers maximum flexibility at the expense of performance, power consumption, and area utilization. Users can determine what processor functionality they need for their specific design and synthesize a single processor core, or multiple processor cores — 8-bit, 16- bit or 32-bit MCU, MPU, or DSP — into the programmable logic in their designs. This, however, means they have to give up programmable logic element real-estate and design around the core they implement in their design. And in designing around the soft MPU, they must also be very mindful of timing constraints and power budgets, which can change depending on what applications are ultimately run on the microprocessor — a task which, unfortunately, typically comes after the hardware has been designed.