The rad-hard and rad-tolerant
reprogrammable Virtex®-
5QV FPGA from Xilinx (San
Jose, CA) supports specified Total
Ionizing Dose (TID) and characterized
Single-Event Effects (SEE). The
space-grade field programmable
gate arrays are also optimized with
embedded MPUs, embedded DSP
elements, built-in Ethernet MAC blocks, and high-speed serial connectivity.
The Rad-Hard and Rad-Tolerant Reprogrammable Virtex®- 5QV
Built on 65nm copper process technology, the Virtex-5QV Space Grade
FPGA provides hardness to Single-Event-Upset (SEU), immunity to
Single-Event Latchup (SEL), and data path protection from Single-Event
Transients (SET). The Virtex-5QV FPGA contains hard-IP system level
blocks, including 36-Kbit block RAM/FIFOs, second generation 25 × 18
DSP slices, SelectIO™ technology with built-in digitally controlled impedance,
power-optimized high-speed serial transceiver blocks for enhanced
serial connectivity, PCI Express®-compliant integrated Endpoint blocks,
and Tri-mode Ethernet MACs (Media Access Controllers).
Each configuration logic block (CLB) in the device contains eight user
registers. Registers are implemented with rad-hard, dual-node latches in
a target-initiator configuration. The Virtex-5QV FPGA input/output
blocks (IOBs) have rad-hard dual-node latch registers in all ISERDES,
OSERDES, ILOGIC, and OLOGIC blocks.
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