Using Event Systems and DMA to Cut Power Consumption

The trick to exploiting the ultra lowpower characteristics of microcontrollers with 100 nA sleep mode power consumption is to keep them in sleep mode as much as possible. The problem is that the growing number of on-chip peripherals and the increasingly dataand interrupt-intensive nature of modern applications make this a very difficult objective to achieve.

As embedded applications become more responsive to their environments, the number of peripherals that capture and process environmental data is increasing rapidly. It is commonplace for microcontrollers to have ADCs, DACs, PWMs, multiple timer/counters and numerous I2C, SPI, CAN, USB and USART interfaces for communications. In addition, the number of interrupts and amount of data that must be moved between the memories and the peripherals has grown exponentially, increasing the CPU load and consuming more power. The context switching and interrupt usage for two simultaneous interperipheral communications and a single 64 Mbps data transfer requires 200 CPU MIPS and consumes 100 mA.

Peripheral signals often do not require the CPU to do anything except let another peripheral know it needs to do something. Unfortunately, liaising between two peripherals requires cycle intensive interrupt processing. For example, in a motor control application, overheating is prevented by constantly measuring the current on the motor and toggling an analog comparator when an overcurrent situation signals that the motor has stalled. The CPU is interrupted and shuts down the pulse width modulator (PWM) output for the motor driver. This process can require tens of cycles, and another 20-100 cycles to restore the context. The microcontroller is not really doing anything that requires its processing capabilities; it is basically just passing a message from an analog comparator to a PWM output. The cycles are basically wasted.

Other cycle wasters include the use of timer/counters to time other peripherals such as ADCs and DACs. In these situations, an interrupt is generated to start every conversion. At a sample rate of just a few kHz, these timer/counter interrupts consume over 1 MIPS — about 8% of a 12 MIPS MCU’s capacity.

One solution to this problem is to use a microcontroller with an event system and DMA that off-load these functions from the CPU. Ultra-low-power, single-cycle RISC 8/16-bit MCUs are available with multi-channel event systems and DMA controllers that allow the simultaneous execution of up to 8 inter-peripheral events, plus up to four 64 Mbps data transfers, while consuming less than 10 mA. Since the event system and DMA allow the peripherals to communicate with each other autonomously, no CPU clock cycles or interrupts are required. The CPU can be put into idle sleep mode.