Improved Signal Chains for Readout of CMOS Imagers

Two major imitations of prior readout signal chains are overcome.

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower and operational-amplifier-based amplifier circuits.

The improved design affords the best features of prior source-follower-and operational-amplifier-based designs while overcoming the major limitations of
those designs. The limitations can be summarized as follows:

• For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, non-linearity, and reduced small-signal gain.

• For an operational-amplifier-based signal chain, the required bias current and the output noise increase super-linearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

The improved design (see figure) provides a switched source follower in each column, one each for the signal and reference samples [denoted an in-column switched source follower (ICS²F)], followed by a single capacitive transimpedance amplifier (CTIA) gain stage. The ICS²F consists of a different configuration of the column-selecting FET such that no DC bias current flows through it, and hence, without the associated ohmic voltage drop. Unlike in a prior operational-amplifier-based design involving direct connection of the sample and hold capacitors to the row-bus, the input terminals of the amplifier present CTIA gain stage are not in direct contact with the bus and, therefore, this stage produces voltage gain without the bandwidth reduction and noise multiplication that is caused by the Miller effect. Secondly, as a result of using ICS²F, the bus carries a predominantly voltage signal, (as opposed to a predominantly charge signal as in a prior operational-amplifier-based signal chain). Hence, the charging and discharging of the bus is not slowed by the Miller effect, enabling reduction of the bias current from the value that would otherwise be needed. The elimination of the ohmic drop across the column-selecting switch reduces the output voltage offset to a minimum, eliminates nonlinearity, and makes the small-signal gain approach its ideal value of unity.

This work was done by Bedabrata Pain, Bruce Hancock, and Thomas Cunningham of Caltech for NASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
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Refer to NPO-42006, volume and number of this NASA Tech Briefs issue, and the page number.