Medical imaging is an information processing technique that takes data samples from medical devices such as magnetic resonance imaging (MRI) or computer tomography (CT) scanners and translates them into 2D, 3D or even 4D images. Advances in sensor technology allow for the generation of an increasing number of images per procedure and per patient, posing a tremendous challenge for the efficient, in-time processing and visualization of the resulting images. In addition, sensor systems are now capable of acquiring thousands of projections per second, literally flooding the image reconstruction subsystem with several hundreds of Mbytes of data per second.

CT is used in a growing number of clinical applications, and keeps challenging the scientific community to continuously propose new algorithms with improved image quality while reducing the X-ray dose. With modern algorithms, every single voxel in the reconstructed volume requires hundreds of processing cycles on a given processor. Combining the processing requirements with the high-input data rate, CT also challenges manufacturers to design computer systems that enable the object to be reconstructed within a timeframe compatible with the workflow in a hospital, while keeping costs reasonable. The implied tradeoffs have often led to the use of approximate methods such as Feldkamp-type algorithms for flat panel, detector-based systems used in C-arm CTs or micro-CT. However, keeping the reconstruction times acceptable has also forced the design of special-purpose reconstruction platforms based on field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

The Cell Broadband Engine Processor
Originally developed for the gaming industry by IBM, Toshiba and Sony, the industry-leading Cell microprocessor technology is under development for use in medical, defense, and commercial applications, mainly because the Cell technology offers significant performance improvement compared to other available technologies. The Cell Broadband Engine (CBE) architecture is essentially a multicomputer- on-a-chip, representing the integration of multiple processor cores on a single die. The CBE consists of one IBM 64-bit Power Architecture core, called the power processing element (PPE), and eight specialized co-processors called synergistic processing elements (SPEs). The PPE can be considered as an implementation of a PowerPC processor with the traditional hardwired L1 and L2 caches. The SPEs are oriented toward parallel vector processing, using a novel single-instruction, multiple-data (SIMD) operating architecture.