| Cell Technology Tackles 3D Medical Imaging Reconstruction Challenges |
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| Sep 01 2007 | |
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advertisement: The SPEs do not possess traditional cache hardware. Instead, multiple levels of memory hierarchy must be explicitly managed by software. All nine cores in the CBE are interconnected by a coherent on-chip element interconnect bus (EIB). The EIB also connects to the memory controller, the I/O interface and the coherence interface. The memory controller and the I/O interfaces give all processing elements access to main memory and I/O space while the coherence interface allows for building multiprocessor systems in symmetric multiprocessor mode. The Cell architecture enables all kinds of distributed applications to run on the processing units, using elaborate data-transfer techniques to design any combination of parallel/pipelined approaches. Therefore, all applications that have the ability to subdivide the main tasks can be subdivided into a finite number of subtasks, and take advantage of the immense processing power implemented in the Cell processing elements while keeping the datatransfer latency very low. Clocked at 3.2 GHz, the Cell processor offers a peak performance of 204.8 GFLOPS from the set of eight SPEs running, and a memory bandwidth of 25 Gbytes/s which is significantly higher than any off-the-shelf solution. The EIB is capable of peak data rates of ~200 Gbytes/s. This ground-breaking level of extreme performance, coupled with the vector processing capabilities of the SPEs, make the CBE capable of delivering dramatic new capabilities to embedded applications that rely upon computationally intense processes such as Fast Fourier Transforms (FFTs), matrix operations or backprojection algorithms.The Cell Processor: Challenging Software Development The challenge of the CBE lies in the complexity of its design. Without software tools, this complexity puts a substantial burden on any programmer. To be suitable for broad use in embedded applications, the CBE needs a layer of software to help programmers distribute processing among multiple cores, as well as manage use of the multiple levels of memory. Mercury Computer Systems developed the MultiCore Framework (MCF), which provides an abstract view of CBE operations, oriented toward computation of multidimensional data sets. With MCF, the programmer has explicit control over how data and processing is divided among processor cores and memory elements while being insulated from specific hardware details. The key innovation in MCF is something called the data-distribution object, which is a way of describing an n-dimensional matrix data set in such a way that it can be processed in small chunks, or tiles, by one or more workers. For each data set, the manager program specifies a set of parameters for each distribution object, such as number of dimensions, size of dimensions, tile size, packing order and data types. |
