Home arrow Features arrow Modeling System Architecture and Resource Constraints Using Discrete-Event Simulation
Modeling System Architecture and Resource Constraints Using Discrete-Event Simulation Print E-mail
Sep 01 2008
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The terminator, T-junction, and cable blocks at the bottom of the model represent physical components of the bus.

Standard Ethernet networks use a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol to manage use of the shared channel. The binary exponential backoff algorithm for this model is implemented in the MAC Controller subsystem. In this setup, all applications transmit at an average rate of 100 packets per second and the packet size varies from 64 bytes to 1500 bytes. Upon simulation, we can visualize the utilization of the Ethernet bus, the throughput for a particular computer, and the average latency for message transmission. Figure 2 shows the overall channel utilization, or the proportion of time that the channel is in use.

Channel utilization is low, indicating that the bus might be able to support additional traffic. We can now incorporate the traffic from additional devices into the model and study their effect on overall channel utilization and the throughput of individual devices.

Real-Time Operating System with Prioritized Task Execution

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Figure 2. Channel utilization.

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This example models the prioritized task execution in an RTOS. Tasks with different priority levels share the processor in such a system. Typical tasks include low-priority application tasks in the main loop of the RTOS and highpriority interrupt tasks that invoke interrupt service routines (ISRs). Execution of interrupt service routine delays the processing of application tasks.

Ideally, the number of tasks waiting in the task queue should not increase and the RTOS should return to the idle task to avoid excessive processing delays. How can we verify that the RTOS in this example satisfies this requirement?

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Figure 3. Operating system with prioritized task execution.

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To answer this question we must model the shared processor and its interaction with various tasks. Speci - fically, the model should demonstrate priority-based task execution and preemption. Figure 3 shows the SimEvents model of such a system.



 

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