| Multi-Cores: The Gateway to Next-Gen SBCs and Blades |
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| Intel | |
| Mar 01 2007 | |
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Page 2 of 2 While Intel’s software tools can be used for asymmetrical and symmetrical multiprocessing, SMP can simplify life for both the developer (because only one set of tools is required) as well as the underlying system, which uses fewer resources. By uniformly executing instructions on the same set of identical processors, both cores can be better optimized to maximize the use of processing resources either on one core or recovered from the other. More importantly, while SMP supports programming models used on an asymmetric processor, it also ports easily over to the computeintensive sets of instructions typically used in multimedia applications. In this sense, SMP has enabled multi-core technology to greatly enhance media or signal processing capabilities. Real-time multimedia software can run more efficiently on parallel processor architecture to achieve higher performance, lower cost, and lower power. From a hardware point of view, multicore processors simply are single-die physical units residing side-by-side that provide capabilities similar to traditional SMP machines. Along with the components typically associated with dual-core platforms such as the front-side bus (FSB), cache, high-bandwidth data paths, and additional DMA controllers, dual-core processor designs each physical processor sharing the on-die cache, thereby greatly reducing the number of cache misses and improving performance. In addition, the latest dual-socket designs leveraging Xeon LV 5138 support dual independent buses (DIBs), thereby allowing a relatively large amount of cache support across the Intel 5000 chipset family through the use of cache coherency. The end result is a new level of performance and power efficiency for compute- and I/O-intensive designs. Manufactured globally through an industry-leading 65-nm fab process, the new Intel Core Microarchitecture-based processors feature execution pipelines that are 33% wider in each core than previous generations. Benefits include:
The Intel NetStructure MPCBL0050 blade server delivers almost three times the performance per slot of the leading competitive blade server, which enables service providers to deliver new, revenuegenerating services with fewer blades. It runs Carrier Grade Linux operating system and offers significant performance improvements for compute-intensive and database-access applications, including IP Multimedia Subsystems (IMS), wireless control plane, and IPTV. Additionally, it is designed to be the first blade server to comply with the proposed Communications Platforms Trade Association (CP-TA) 1.0 standard to improve industry interoperability. As network operators, service providers, and ISVs continue their relentless quest for the next “killer app” — whether it be voice, video, data, or wireless services — they will undoubtedly turn to parallel processing more and more to meet their power and performance requirements. And while parallel processing remains at a nascent stage, Intel intends to build upon its 30-year legacy with the promise of further advancements similar to its milestones in dual-core processing as it continues to march down the path of multi-core. This article was written by Eric Mantion of the Embedded and Communications Group of Intel, Santa Clara, CA. For more information, contact Mr. Mantion at This e-mail address is being protected from spam bots, you need JavaScript enabled to view it , or visit http://info.hotims.com/10964-401. Prev: SOA in Practice: Model-Driven Repositories Fill the Gap Between Concept and Implementation Next: Beamforming System Eases Crowded Wireless Spectrum |
