SRIO is a point-to-point switched serial technology featuring:

• 1.25, 2.5, or 3.125 Gbps signaling rate

• A SRIO port with 1 or 4 lanes for a maximum data rate of 1.25 GBps per port in each direction

• 8 B/10 B encoding and end-to-end packet CRC

• Four levels of priority

• Support for multi-cast

• Support for global memory

• Support for redundant routes for high-availability applications

• Messaging and doorbell features for efficient inter-processor exchanges

Curtiss-Wright’s CHAMP-AV6 Quad PowerPC 8641 DSP board is an example of the next generation of modules taking advantage of the high-speed connectors for the VPX format to harness the bandwidth advantages of the SRIO fabric.

PCIe in Mil/Aero

The mainstream PCI Express (PCIe) interface—the same fabric as commonly used in current desktop, laptop, and server PCs—is now finding its way into advanced single-board computer and digital signal processing modules targeted for deployed mil/aero applications. The widespread use of PCIe in volume PC applications drives down the cost of PCIe switches and PCIe peripherals, making cost effectiveness one of its major benefits. Despite approaching commodity status in the PC world, PCIe incorporates a number of sophisticated technical features that together make it one of the most advanced fabrics currently available.

Some of the key features of PCIe include:

• Communications are point-to-point. Each link (point-to-point connection) can consist of 1, 2, 4, 8, 16, or 32 lanes.

• Each lane consists of one transmit (Tx) and one receive (Rx) pair signaling at 2.5 Gbaud, yielding a nominal data rate of 250 MBps in each direction per lane, or an aggregate data rate of 4 GBps for a typical 8-lane link.

• 8 B/10 B encoding of each data byte and end-to-end CRC on each packet provides robust error detection.

• A packet acknowledgement protocol with automatic retransmission on errors provides end-to-end reliable data transmission with no software overhead.

• Prioritization of data flows (“quality of service”).

• Physical layer incorporates bit scrambling to reduce EMI (by eliminating long sequences of 1s or 0s that create a square wave).

• The electrical signaling layer incorporates pre-emphasis/deemphasis to optimize signal integrity, allowing lower cost materials to be used for printed circuit boards and connectors.

The advanced technical features of PCI Express, its wide adoption in the general IT industry, and its software compatibility with the ubiquitous conventional PCI standard make it a natural choice for incorporation in high-performance embedded mil/aero computing systems.

As illustrated by the discussion above, new serial switched fabric technologies are enabling mil/aero embedded computing systems to achieve new levels of functional density while reducing system cost and weight (see Figure 2). Of the panoply of existing and emerging fabric technologies, three stand out as offering particular benefit—GbE as the standard bearer of IP-based data traffic whether on intra-platform networks or within a standard backplane-based subsystem; SRIO for interconnecting dense multi-computing clusters for DSP applications; and PCIe for core processor-to-peripheral highbandwidth data flows.

This article was written by Stewart Dewar, product marketing manager. at Curtiss- Wright Controls Embedded Computing, Modular Solutions Group, Ottawa, ON, Canada. For more information, contact Mr. Dewar at This e-mail address is being protected from spam bots, you need JavaScript enabled to view it , or visit http://info.hotims.com/10958-400.