Automating Radiation Effects Mitigation with FPGA Synthesis

FPGA designers of aerospace and defense applications have long wrestled with radiation effects. More recently, due to shrinking technology nodes, concerns have arisen about radiation-related upsets in other safety- or mission-critical applications such as medical devices, networking gear, and commercial avionics. Smaller geometries in FPGAs mean that an energetic particle can more easily alter the current flow and charge storage of a device’s configuration SRAM. In fact, policymakers for DO-254, the design assurance standard for airborne hardware, are now encouraging hardware designers to examine and address radiation-effects issues through mitigation techniques.

Through the years, FPGA designers have acquired an increasing array of tools and methods to address radiation effects. Rad-tolerant silicon is one viable approach. Another is board- or device-level redundancy, where a soft error in one unit is voted out by the other two units. A third approach is hand-coding mitigation circuitry, where the FPGA developer incorporates circuitry such as triple modular redundancy (TMR) or safer finite state machines (FSMs) at the hardware description language (HDL) level. Each method has its tradeoffs in terms of cost, schedule, safety, and quality-of-results. For example, rad-tolerant silicon is substantially more expensive than its commercial counterpart. Device-level triplication adds various types of overhead including cost, area, and power. And hand coding requires high levels of expertise, it’s time consuming, and it can result in hard-to-detect errors.

Recently introduced technology automatically incorporates advanced mitigation circuitry during device-neutral RTL synthesis, thereby providing additional protection through the implementation flow itself. This way designers and project managers can more flexibly select the most suitable (or lower cost) silicon for their application, include adequate safeguards against a variety of radiation effects, avoid the overhead of board- or device-level redundancy, and reduce the risk of human error from hand-coded mitigation. With support for SRAM, flash, and antifuse architectures, this new technology can accelerate the development schedule, expand device options, and reduce production cost. However, as with most automatic implementation approaches, designers should ask: How does this technology work? And how can I verify it?